Recent reference voltage circuits for grayscale or opposite electrode application in liquid crystal displays are required to be capable of 9 or greater bit outputs and high precision monotonicity. Resistor-string D/A converters used in these reference voltage circuits are advantageously generally suitable for high speed operation and readily provides monotonicity. For 9 or greater bit outputs, however, the resistor-string D/A converter is not practical because of its increased number of wires (512 wires for 9 bit outputs), resistors, and switches.
FIG. 6 is a circuit diagram of a conventional resistor-string D/A converter 100. The D/A converter 100 includes a resistor-string circuit 101 producing divided voltages from reference voltages VH and VL and a switching circuit containing switches for switching between divided voltage outputs vref<0> to vref<(2^n)−1>.
An analog output voltage Vout obtained by conversion of an n-bit digital signal is given by equation (1):Vout=VL+(VH−VL)*k/2^n  (1)where k=0 to 2^n−1.
The digital signal fed to the D/A converter 100 consists of n upper bits HoB<n−1:0> and m lower bits LoB<m−1:0>.
The D/A converter 100 in FIG. 6 is not practical for high bit output applications due to an increased number of wires, resistors, and switches. For example, for n=9 (9-bit conversion), the D/A converter 100 needs 512 wires, 512 resistors, and 512 switches. Likewise, for n=10 (10-bit conversion), the D/A converter 100 needs 1024 wires, 1024 resistors, and 1024 switches.
FIG. 7 is a circuit diagram of another conventional resistor-string D/A converter 103. The D/A converter 103 is disclosed in Japanese Patent Application Publication, Tokukaihei, No. 6-224767 (Publication Date: Aug. 12, 1994, Patent Literature 1).
The D/A converter 103 includes a D/A converter 104 producing a reference voltage VH_1 in accordance with n upper bits HoB<n−1:0> for output, a D/A converter 105 producing a reference voltage VL_1 in accordance with the n upper bits HoB<n−1:0> for output, a resistor-string circuit 106 producing divided voltages from reference voltages VH_1 and VL_1 in accordance with m lower bits LoB<m−1:0>, and a switching circuit 107 switching between divided voltage outputs vref<0> to vref<(2^m)−1>.
The digital signal fed to the D/A converter 103 consists of the n upper bits HoB<n−1:0> and the m lower bits LoB<m−1:0>.
An analog output voltage Vout obtained by conversion of an (n+m)-bit digital signal consisting of n upper bits and m lower bits is given by equation (4) (derived from equations (2) and (3)):
                              VH_          ⁢          1                =                  VL          +                                    (                              VH                -                VL                            )                        *                                                            (                                      1                    +                    1                                    )                                /                2                            ⋀              n                                                          (        2        )                                          VL_          ⁢          1                =                  VL          +                                    (                              VH                -                VL                            )                        *                                          1                /                2                            ⋀              n                                                          (        3        )                                                                    Vout              =                            ⁢                                                VL_                  ⁢                  1                                +                                                      (                                                                  VH_                        ⁢                        1                                            -                                              VL_                        ⁢                        1                                                              )                                    *                                                            k                      /                      2                                        ⋀                    n                                                                                                                          =                            ⁢                              VL                +                                                      (                                          VH                      -                      VL                                        )                                    *                                                            1                      /                      2                                        ⋀                    n                                                  +                                                                                                      ⁢                              {                                                                            (                                              VH                        -                        VL                                            )                                        *                                                                                            (                                                      1                            +                            1                                                    )                                                /                        2                                            ⋀                      n                                                        -                                                                                                                                        ⁢                                                      (                                          VH                      -                      VL                                        )                                    *                                                            1                      /                      2                                        ⋀                    n                                                  }                            *                                                k                  /                  2                                ⋀                n                                                                                        =                            ⁢                              VL                +                                                      (                                          VH                      -                      VL                                        )                                    *                                                            1                      /                      2                                        ⋀                    n                                                  +                                                                                                      ⁢                                                (                                      VH                    -                    VL                                    )                                *                                                      1                    /                    2                                    ⋀                  n                                *                                                      k                    /                    2                                    ⋀                  m                                                                                                        =                            ⁢                              VL                +                                                      (                                          VH                      -                      VL                                        )                                    *                                                                                    {                                                                              1                            *                                                          2                              ⋀                              m                                                                                +                          k                                                }                                            /                      2                                        ⋀                                          (                                              n                        +                        m                                            )                                                                                                                              (        4        )            where k=0 to 2^m−1 and 1=0 to 2^n−1.
Equations (2) and (3) differ in “1+1” and “1”. The reason is that the D/A converter 104 receives a digital signal input containing the n upper bits HoB<n−1:0> and produces a reference voltage VH_1 that is equivalent to the digital signal containing the n upper bits HoB<n−1:0> plus 1 for output, whereas the D/A converter 105 receives a digital signal input containing the n upper bits HoB<n−1:0> and produces a reference voltage VL_1 that is equivalent to the digital signal containing the n upper bits HoB<n−1:0> for output.
To obtain equations (2) and (3), the D/A converter 104 and the D/A converter 105 may be the same D/A converters so that the D/A converter 104 can receive a digital signal input containing the n upper bits HoB<n−1:0> plus 1 and the D/A converter 105 can receive a digital signal input containing the n upper bits HoB<n−1:0>.
For example, for n=2 and m=7 (9-bit digital signal conversion), the D/A converter 103 in FIG. 7 needs 128 wires, 128 resistors, and 128 switches. Likewise, for n=2 and m=8 (10-bit digital signal conversion), the D/A converter 103 needs 256 wires, 256 resistors, and 256 switches. The D/A converter 103 in FIG. 7 needs fewer wires, resistors, and switches than the D/A converter 100 in FIG. 6.
The D/A converter 100 in FIG. 6 is not practical for 9 or greater bit output applications because of its increased number of wires, resistors, and switches.
Although the D/A converter 103 in FIG. 7 needs fewer wires, resistors, and switches than the D/A converter 100 in FIG. 6, the D/A converter 103 needs the D/A converters 104 and 105 to produce the reference voltages VH_1 and VL_1 respectively before the resistor-string circuit 106, which adds to circuit size. Furthermore, the provision of the D/A converters 104 and 105 could lead to undesirable increases in current consumption and degradation in precision of D/A conversion.